Precision M65 Laptop - Processor Details

As with most Dell systems, this laptop can be purchased with one of several different CPU's. This page generally will only apply to those of you with a processor similar to mine - an Intel® Core 2 T7200, aka 'merom'. However, if you send me details of your system setup, I'll add details here.

> cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz stepping : 6 cpu MHz : 2000.000 cache size : 4096 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 2 fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm bogomips : 3994.16 clflush size : 64

> /usr/local/bin/cpuinfo Processor Information Model: Intel Core 2 T7200, 1.99 GHz Package: 2 Cores Processor Caches L1 code cache, 32 KB L1 data cache, 32 KB L2 unified cache, 4 MB

sep dts acpi ht pbe lm constant_tsc pni monitor ds_cpl est xtpr lahf_lm

Processor Features

General

Scalar

Vector

Addressing

Monitoring

Other

clflush
fxsr
msr Model-specific_register
-senter-
vmx Intel Virtualisation Technology (VT)

cmov
cx8
cx16
fpu
-amd64-

mmx MMX Technology

mmx+

sse SSE Technology
sse2 SSE2 Technology
sse3 SSE3 Technology (Prescott New Instructions)

mtrr
pae
pat
pge
pse
pse36

tm
tm2 Thermal Monitoring 2

tmsc

tsc Time_Stamp_Counter

apic
de

mca
mce
nx Execute Disable (Intel XD)
ss
vme

  64bit 64-bit instructions

simd SIMD instructions (x86)

  -- x86-specific features --
  cmov Conditional Moves 
  mmx  
  sse  
 sse2 
 sse3 
 ssse3 SSSE3 Technology (Merom New Instructions)
  vmx 
  lm Long Mode (64-bit capable) 
  lahf_lm LAHF/SAHF Supported in 64-bit mode
  tm Thermal Monitor 
  tm2 Thermal Monitor 2 
  eist Enhanced Intel Speedstep Technology
  nx

Program Compilation

NB: Everything I have is compiled under GCC. As I do not have access to any alternative compiler (in particular, the Intel C++ compiler), I cannot post any benchmarks in comparison.

The T7200 is a relatively new processor - so you will need at least GCC v4.3.x to take advantage of SSSE3 Merom instruction set. Though there has been some debate in various forums as to the 'best' compilation flags to set, these are the flags I am currently using:

   CFLAGS="-march=core2 -Os -pipe"
 CXXFLAGS="${CFLAGS}"

Several runs of Acovea were tried. Sadly, I am not entirely sure my results, so there may well be other flags worth using.

Frequency Adjustment or 'SpeedStep'

Supported. Uses module acpi_cpufreq. The CPU Frequency Governor is altered through /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor (for cpu0 - alter appropriately for cpu1). A utility for automatically setting this can be found here.

Core Voltage Adjustment aka UnderVolting.

Several methods seem to be available in principle:

Hard code the CPU voltage in the kernel source.
Linux-PHC
CPUPoWer

Not attempted yet. Requires kernel patch.

Microcode Update

It is possible to update the processor microcode. Everything seems to work OK, though I have no way at the moment of testing whether it makes any difference at all. However, as with any processor, it has bugs. Intel tell me that the Merom is NOT affected by the Core 2 bugs. It may, however, have others that are fixed by a microcode update.

CPU Monitoring

This took ages to sort out - simply because I made an incorrect assumption. You need to have kernel support for the ISA bus! Then you can modprobe coretemp, and receive CPU thermal information through sensors. Alternatively, you can access the same information through ACPI, without the ISA support.

Questions

What is the 'best' I/O scheduler? As the CPU supports HyperThreading, is there a benefit in using it? How is it activated? What benefits/costs does Kernel IRQ balancing have? What memory model is best?

Undervolting Tutorial